The present invention relates to a semiconductor device, and that is effective when utilized in circuits for example performing analog-digital conversion.
Recent years have seen much progress in the miniaturizing of electronic devices such as handheld devices which have increased demands for miniaturizing and energy-saving of components mounted in these types of electronic devices. On the other hand, developments in information processing technology have also increased needs for higher accuracy in analog-digital converters that convert analog signals to digital signals. There is accordingly an increasing need for small and high-accuracy analog-digital converter.
One technology for analog-digital conversion that allows miniaturization is known as time-to-digital-converter (TDC). A voltage controller is disclosed for example in Japanese Patent Registration No. 4545439 (corresponding to International Patent Application Publication No. WO003050637 (A2)). This voltage controller includes an analog-digital converter (ADC), a compensator (300), and a modulator (400). The analog-digital converter (ADC) converts analog inputs to digital inputs. The compensator (300) contains a lookup table (302), and sets the digital control signal (154) based on the digital error signal. The modulator (400) supplies a power supply control signal (156) in response to the digital control signal that was set. This voltage controller regulates the output voltage of the switching power converter that has a switching period. The analog-digital converter (ADC) includes a delay line analog-digital converter (700) containing a delay cell array (740). The delay cell array (740) contains plural delay line cells. A detection voltage supply (108) coupled to the delay line analog-digital converter is provided in order to sample the detection voltage once during each switching period of the switching power converter. A reference voltage supply (106) coupled to the delay line analog-digital converter is provided. A test voltage supply (704) coupled to the delay line analog-digital converter is provided. A switch is provided to synchronize the detection voltage and reference voltage with the switching period of the switching power converter, and selectively supply the voltages to the delay line analog-digital converter. Plural taps (752, 754) are provided to measure the extent of propagation of the test signal along the delay line. A calibrator is provided. The calibrator sets the difference between the extent of propagation of the test signal along the delay line when a reference voltage was supplied to the delay line analog-digital converter, and the extent of propagation of the test signal along the delay line when a detection voltage was supplied to the delay line analog-digital converter; within the switching period of the switching power converter. A digital error signal indicating the difference between the detection voltage and the reference voltage is then supplied. A calibrator is provided to set the difference between the extent of propagation of the test signal along the delay line when a reference voltage was supplied to the delay line analog-digital converter, and the extent of propagation of the test signal along the delay line when a detection voltage was supplied to the delay line analog-digital converter; within the switching period of the switching power converter, and supply a digital error signal indicating the difference between the detection voltage and the reference voltage. The relevant digital error signal is supplied to the compensator in order to set the digital control signal. Each of the delay cells in the delay line analog-digital converter is reset within the switching period of the switching power converter.
A related technology for a semiconductor device is disclosed in Japanese Patent Registration No. 4575420 (corresponding to U.S. Patent Application Publication No. US2009146630 (A1)). This semiconductor device includes a switching power supply circuit, a digital control circuit, and a dead-time setter circuit. The switching power circuit includes two semiconductor switching elements coupled in series. The digital control circuit supplies the switching pulses to the semiconductor switching elements in order to switch the semiconductor switching elements on and off. The dead-time setter circuit sets the dead time in which both of the two semiconductor switching elements are off. The dead-time setter circuit includes a delay generator circuit, a selector circuit, and a delay adjuster circuit. The delay generator circuit contains plural delay elements whose delay values are mutually different and coupled in series from the initial stage to the final stage in the order of small delay value, and whose total delay value is smaller than the pulse signal cycle input to the initial stage. The delay generator circuit delays the rising edge of the output signal of each delay element by conveying the pulse signal in sequence from the initial stage to the final stage, relative to the rising edge of the pulse signal, to generate pulse edges where the cycle of the pulse signal is split into plural cycles. The selector circuit is input by the output signals of each delay element, and outputs one output signal selected from among the output signals to the digital control circuit as a signal for setting the dead time. The delay adjuster circuit selects an output signal from among the output signals from each delay element, to set the duty cycle of the switching pulse to a minimum, and outputs that (output) signal to the selector circuit.